During chip design, computer simulators such as circuit simulators, field simulators, and hierarchical field simulators are used to model electrical, magnetic, and physical behavior of circuit models. Circuit simulators verify circuit designs and predict general circuit behavior. As shown in FIG. 1, a circuit simulator uses a predefined circuit model (10) (a listing of components, attachments, and known properties of the circuit) to run a circuit simulation (12). The circuit simulation (12) calculates electrical, magnetic, and physical aspects of the circuit design not defined in the circuit model (10), and then produces an output file (14) containing properties given in the circuit model (10) and properties calculated during the circuit simulation (14).
An example of a circuit simulator well known in the art is HSPICE (produced by Avant!). Field simulators and hierarchical field simulators are used primarily to simulate electromagnetic interaction in a circuit (one aspect of circuit behavior). A hierarchical field simulator simulates electromagnetic interaction in hierarchical circuit models (circuit models that have been abstracted into layers). Two examples of hierarchical field simulators are IES3 (produced by Bell Labs) and FastHenry (produced by Massachusetts Institute of Technology).
A circuit printed on an IC is made up of electrical devices such as transistors, i.e., nonlinear elements and wires which connect the electrical devices (known as connecting wires). Wire delay, i.e., the amount of time a signal takes to travel through a connecting wire, is a type of circuit behavior that is approximated with a computer simulator. It is important to know wire delay in a circuit because large amounts of wire delay can adversely affect the operation of the circuit. In order for a computer simulator to approximate wire delay, a connecting wire must be translated into some type of circuit model. In many cases, the connecting wire is translated into a circuit model having resistors and capacitors.
FIGS. 2a and 2b depict the steps of a typical process by which a connecting wire is translated into a resistor and capacitor circuit model. In FIG. 2a, a connecting wire having an “in” node (62) and an “out” node (64) has been split into three conductor segments by inserting two nodes (66, 68) onto the connecting wire. In FIG. 2b, the capacitance and resistance associated with each conductor segment is then modeled by inserting capacitors (72) and resistors (70) into the connecting wire. A capacitor (72) is attached to each node (62, 64, 66, 68) and a resistor (70) is inserted between each pair of nodes (62 and 66, 66 and 68, and 68 and 64). The values of the capacitors (72) and the resistors (70) are ascertained either from a lookup table or from a field simulator, after which, the circuit behavior is modeled using a circuit simulator.
Due to increasing operation frequency within electronic devices, the simple capacitor and resistor circuit model given in FIG. 2b is no longer an accurate model of the wire delay in a connecting wire. For example, the contribution that inductive interaction, i.e., electromagnetic interference, between the conductor segments makes to the wire delay must now be accounted for in the circuit model. Inductive interaction is caused by electromagnetic fields that are produced by current flowing through conductor segments in close proximity with one another. As shown by the circuit model in FIG. 2c, the wire delay caused by inductive interaction between conductor segments is modeled by inserting inductors (74) into the capacitor and resistor circuit model shown in FIG. 2b. An inductor (74) is inserted between each pair of nodes (62 and 66, 66 and 68, and 68 and 64) in series with the resistor (70) located in the same conductor segment. The values of the inductors (74) are ascertained either from a lookup table or from a field simulator.
In addition to the wire delay contributed by inductive interaction between the conductor segments, inductive interaction between the inductors in the conductor segments (known as coupling inductances) contributes wire delay to the circuit model. In a connecting wire represented by “N” conductor segments, there are N(N−1)/2 inductive couplings. For example, the connecting wire represented by the circuit model in FIG. 2c has three conductor segments, and, therefore, has 3(3−1)/2, or three, inductive couplings. The values of these inductive couplings, i.e., the coupling inductances, are calculated using a lookup table or a field simulator, after which, the circuit behavior is modeled using a circuit simulator. In circuit models having a large value for “N,” heuristic assumptions, i.e., only large coupling inductances taken into account, are used to eliminate some or all of the inductive couplings from the circuit model. However, simply neglecting some or all of the inductive couplings may lead to an unstable circuit model whose wire delay may no longer correspond to the actual wire delay of the connecting wire being modeled.
Normally, a circuit simulator is not used to calculate coupling inductances because a lookup table or a field simulator takes less time to calculate inductive interaction. However, it is important to note that, although coupling inductances are often calculated using a lookup table or a field simulator, coupling inductances can also be calculated using a circuit simulator. Usually, a lookup table, a field simulator, and a circuit simulator store coupling inductances for a particular circuit model as a square matrix having a row and column dimension of “N.” For example, in a circuit model having “N” conductor segments, the coupling inductances (“K”) are stored in a square matrix as such:
  K  =      [                                        K            11                                                K            12                                    ⋯                                      K                          1              ⁢              N                                                                        K            21                                    ⋯                          ⋯                          ⋯                                      ⋯                          ⋯                          ⋯                          ⋯                                                  K            N1                                    ⋯                          ⋯                                      K                          N              ⁢                                                          ⁢              N                                            ]  In a circuit model with a large value for “N,” i.e., several conductor segments, the square matrix used to store the coupling inductances requires a large amount of storage space in memory.
In hierarchical field simulators, coupling inductances are represented as the product of two matrices, where one of the matrices represents electrical effects that contribute to inductance and the other matrix represents magnetic effects that contribute to inductance. The matrix representing the electrical effects, an “electrical matrix,” shows the voltage present in the conductor segments. The matrix representing the magnetic effects, a “magnetic matrix,” shows the current present in the conductor segments. The longer dimension (row or column) in the electrical matrix and the magnetic matrix indicates the conductor segments in each of the two matrices. If the longer dimension is a row, then each row in the matrix represents a conductor segment, however, if the longer dimension is a column, then each column in the matrix represents a conductor segment.
If “K” is used to represent a matrix of coupling inductances, and “A” and “B” are used to represent an electrical matrix and a magnetic matrix, then:K=A*B, where
      A    =          [                                                  A              11                                            ⋯                                              A                              1                ⁢                P                                                                          ⋯                                ⋯                                ⋯                                                ⋯                                ⋯                                ⋯                                                              A              N1                                            ⋯                                              A                              N                ⁢                                                                  ⁢                P                                                        ]        ,      B    =          [                                                  B              11                                            ⋯                                              B                              1                ⁢                P                                                                          ⋯                                ⋯                                ⋯                                                ⋯                                ⋯                                ⋯                                                              B              N1                                            ⋯                                              B                              N                ⁢                                                                  ⁢                P                                                        ]        ,                and P<<N and also several entries in A,B=0.Because the total number of elements in “A” and “B” is less than the total number of elements that would be present in “K,” the amount of time/memory space required to compute/store “A” and “B” is much smaller than the time/memory space required to compute/store “K.” Thus, a hierarchical simulator uses less time/memory space to calculate coupling inductances than a lookup table, a field simulator, or a circuit simulator because a hierarchical simulator represents coupling inductances as matrices “A” and “B,” while the lookup table, the field simulator, and the circuit simulator represent coupling inductances as a matrix “K.” This implies that there is an advantage in using a hierarchical simulator to calculate coupling inductances over using a lookup table, a field simulator, or a circuit simulator.        
Because a circuit simulator is typically used during chip design (where a hierarchical field simulator may not be used), it would be advantageous to be able to calculate coupling inductances for connecting wires using a hierarchical field simulator, and then include these values in the circuit model used by the circuit simulator. Unfortunately, the hierarchical algorithm for calculating coupling inductances is hidden inside the hierarchical simulator. This means that the electrical and magnetic matrices cannot be accessed by a circuit simulator. As a result, there is a need for a hierarchical algorithm capable of inclusion in a circuit simulator. This will allow a chip designer to take advantage of the speed and storage capabilities of a hierarchical simulator, while retaining the flexibility of a circuit simulator.